Some of the primary concerns in the manufacture of semiconductor devices are the mechanical and electrical properties of the metallization used to carry electrons within the semiconductor device. As the manufacturing technology of semiconductors becomes more sophisticated, the physical properties of the materials used in semiconductor device, such as the complexity of preferred orientations of polycrystalline microstructures, becomes increasingly important. Crystallographic orientation, grain size and grain morphology play major roles in the reliability, quality assurance, electrical migration resistance, electrical properties, chemical-mechanical polishing (CMP) removal rates, and CMP endpoint detectability. In particular, crystallography plays a role in many aspects of a CMP process, such as the determination of CMP rate curves, the polishing time, the pressure on the wafer and pad, the speed of rotation and the slurry feed rate and chemistry, such as polarity. U.S. patent application Ser. No. 10/121,370, incorporated herein by reference, describes adjusting solvent polarities in a CMP slurry to compensate for differential removal rates.
One of the problems with current manufacturing systems is that process steps within a semiconductor line are treated as discrete steps, which are considered to be independent of the step preceding or following them. CMP is one such step. It is not generally known in the art that chemical mechanical planarization is heavily dependent on the morphological and crystallographic nature of the metal put down during the deposition process.
The crystallographic microstructure can be examined with a variety of techniques. Multiphase two-dimensional mapping of crystallographic and morphological data provides challenges to determine the crystallographic grain orientation, grain size and grain boundaries of a crystalline sample. There are numerous ways of obtaining this information, but each of the methods presents slightly different information that the others do not.
The processing of materials in the semiconductor industry to achieve smaller geometries introduces new problems as the boundaries between grain structures and the orientations of the boundaries become more critical. For example, the conventional method of indexing Kikuchi diffraction patterns over a scanned area is one method of determining both the crystallographic orientation and grain morphology of thin films on sample surfaces. Backscattering Kikuchi Diffraction (BKD) in a scanning electron microscope (SEM) can produce Kikuchi bands from polycrystalline grains approaching the size of the probe diameter. By applying the rules of point group symmetry to the Kikuchi bands, characteristics such as crystallographic grain orientation and grain size within a specimen can be determined.
Grains within polycrystalline materials generally have orientations that vary from grain to grain. This variation, when considered over a bulk specimen area, can lead to the directional grouping of specific crystalline planes with respect to certain crystallographic axes. The “preferred orientation” of a polycrystalline sample refers to an average, or overall, orientation of the grains. Multiple preferred orientations can also exist simultaneously within a sample. The complexity of the preferred orientation of polycrystalline microstructures can be examined with a technique known as Orientation Imaging Microscopy, which analyzes collections of BKD patterns. This technique combines the advantages of point orientation in Transmission Electron Microscopy (TEM) with morphological information over a large enough area to provide statistical relevance.
For example, aluminum deposited by chemical vapor deposition (CVD) deposits in a preferred orientation along a (111) fiber texture normal to a silicon substrate. This geometry is preferred to reduce electromigration. BKD pattern analysis can be used to quantify the quality of the deposition of the aluminum along the preferential crystallographic axis.
The movement of the semiconductor industry to copper metallization will require seed layers and barrier layers made out of tantalum nitride, for example. The deposition of copper by CVD does not seem to exhibit preferential orientation. This results in a variable that can differ between deposited copper films. BKD analysis provides a way of quantifying the films for orientation analysis in a two-dimensional mapping array whereby the preferred grain orientations can be compared from one film to another.
BKD pattern analysis works by collecting a Kikuchi pattern at a specific location on a sample surface, converting the pattern to a Hough space where each line is represented as a spot, and using the angular deviations between the spots to calculate the crystallographic orientation of the crystal at that location. The scanning electron microscope beam or the sample stage is then stepped to the next point and the process is repeated. The stepping occurs in a raster pattern with a fixed step size over the entire scan area. Unfortunately, this method is very time consuming. For example, to acquire a pattern from an area that is 10 square micrometers with a step size of 50 nm, approximately 40,000 individual Kikuchi patterns must be collected and analyzed. With each Kikuchi pattern typically taking approximately 0.5 seconds, this yields a scan time for the entire area of approximately 11 hours.
The pattern also has a maximum grain boundary resolution of 50 nm. The lengthy collection time of these patterns makes automated BKD pattern analysis labor intensive and time consuming. Increasing the step size does decrease the time element involved in obtaining and analyzing date with respect to certain characteristics of a polycrystalline material.
Ion channeling is another technique used, for example, to study defect concentrations in crystals. When an ion beam is aligned along a major crystal axis or plane, ion-atom interaction probability is significantly reduced, resulting in a large reduction of scattering events and deeper penetration of ions into the crystal structure. Accordingly, a secondary electron signal can be detected and analyzed to determine channel locations, and thus some basic morphology of the crystal, for example, by comparison to a reference crystal. Angle resolved channeling (ARC) of crystal planes about different axes can be obtained by adjusting the sample orientation in incremental angular steps. Data is acquired at each angle and an accumulated data set of backscattered spectra at each angle is used to create an image of the crystal structure. The main difficulty with resolving discrete crystallographic information from ion channeling is due to the overlap in contrast intensities for different crystalline orientations.
The foregoing metrological techniques are conducted off-line, i.e., by taking partially fabricated structures in fabrication, including semiconductor devices, out of the manufacturing sequence. However, inline metrology techniques that identify either grain size or preferred orientation of polycrystalline films do not exist. Semiconductor devices are typically destructively measured offline by time consuming techniques of electron diffraction and x-ray diffraction. The disadvantage of these offline techniques is that they are destructive and require constant monitoring on test structures and wafers, which results in a window between when problems occur and when problems are detected.
Current micro-electronics manufacturing methods incorporate metrology methods, such as the methods described above, for the purpose of downstream quality control. For example, once a photoresist process has been completed, it is known to utilize a scanning electron microscope or other metrology technique to measure how closely the photoresist mask corresponds to its intended configuration. A go/no-go parameter may be established, and semiconductor wafers having photoresist patterns that are outside of the acceptance limits are removed from the production line for subsequent rework. Wafers having acceptable photoresist masks are then processed through a further manufacturing step, such as for example, an etching process. A second metrology step may then be used to confirm that the resulting hard mask product falls within predetermined acceptance limits.
In spite of the numerous advances in micro-electronics manufacturing techniques, there remain many aspects of various processes that are not fully understood by those skilled in the art. The control of many micro-electronics manufacturing techniques includes a significant amount of uncertainty. Plasma etch processes are generally difficult to control, with variations occurring from wafer to wafer and from lot to lot. Uncertainties may be induced by machine aging and cleaning lead times, run-to-run variations in wafer attributes, and chemistry of the plasma. Quality control is essentially a feed-back process, i.e. the output product is measured to determine if it is acceptable, and if it is unacceptable, a control parameter is changed. The output product is then again measured to see if the desired corrective effect has been achieved. This cycle is repeated until an acceptable output product is achieved. Each step in the manufacturing process is controlled in a similar manner. For example, to achieve a desired etch pattern, there must first be a photoresist development step then an etching step. Current quality control processes involve a first metrology step on the developed photoresist pattern, then a second metrology step on the etched wafer surface. Each of these steps are treated separately, and each has its own range of acceptable variation from the ideal design value. Because these processes are both complicated and not fully understood, there has been no effort in the industry to integrate the quality control aspects of the overall manufacturing process. Such a control scheme is naturally rigid, allows for the build-up of unfavorable tolerances, and provides no capacity for accommodating deficiencies in one process with counterbalancing variations in another process.
It is known to apply a neural network to the control of a semiconductor wafer etching process. Both U.S. Pat. No. 5,653,894 issued to Ibbotson, et al., and U.S. Pat. No. 5,737,496 issued to Frye, et al, describe the use of neural networks to control the endpoint in a plasma etch process. While such systems provide a degree of in-process control for an etch process, further improvements are desired.